1. Field of the Invention
The present invention relates to a method of monitoring implantation parameters for manufacturing of semiconductor devices using test wafers for obtaining information on ion-implantation characteristics. The present invention, in particular, relates to methods of monitoring ion-implantation of a plurality of ion species having alternating doping polarity or of the same ion species and having variable implantation depth.
2. Description of the Invention
The manufacture of semiconductor devices requires a large number of discrete process steps to create a packaged semiconductor circuit device, starting from a blank semiconductor substrate, which is usually provided as a semiconductor wafer. The semiconductor device manufacturer fabricates semiconductor circuit devices, e.g., microprocessors, DRAM (dynamic random access memory) chips, and ASIC (application specific integrated circuit) chips, and the like, on individual wafers, usually forming a number of devices on each wafer. The individual fabrication processes for semiconductor circuit devices include photolithography, ion-implantation, etching and other associated fabrication processes known in the art. To successfully produce the semiconductor devices with high production yield, all of the above processes must perform reliably according to tight process specifications. To ensure that these processes perform according to the specifications, typically, selected semiconductor wafers, herein referred to as test wafers, are frequently and periodically introduced into the various fabrication processes to control and properly adjust process parameters of these steps.
For the ion-implantation process, implant homogeneity of every implanted ion species across the wafers, which have usually diameters up to 8 inches (20.32 cm) or 12 inches (30.48 cm), is very important. Uniform ion-implantation is required for a high process yield. After ion-implantation has been completed, annealing of such a wafer, e.g., rapid thermal annealing (RTA), is necessary to electrically activate the implanted ions and build the implanted ions into the lattice of the wafer by means of substitution. By electrical activation, the electrical characteristics of the implanted substrate, such as the local electrical sheet-resistance (Rs), are representative of the implantation parameters. Relying on the fact that RTA annealing and its effects on the electrical activation are substantially homogeneous across the whole wafer, homogeneity of every implanted ion species across the wafer, as represented by the local electrical sheet-resistance, is influenced only by the ion-implantation process.
Process specifications are equally tight for all chips produced on a wafer. Therefore, homogeneity of implantation parameters must be ascertained to obtain a high production yield for any chip independent of the location on the production wafer. Monitoring of ion-implantation normally makes use of local electrical sheet-resistance measurements with a four-point-probe technique repeatedly applied to locations distributed across the whole wafer. This type of measurement is well known to the person skilled in the art. The four-point-probe technique measures the resistivity xcfx81 using four probes on a surface of a blank semiconductor wafer. These probes are aligned on a straight line and have a constant spacing s (in cm). A current I (in mA) is passed through the outer probes and a voltage V (in mV) is measured between the inner probes. The measured resistance VI is converted to resistivity xcfx81 (in xcexa9xc2x7cm) according to the commonly known formula
xcfx81=(V/I)27xcfx80s. 
In order to obtain reliable test results, rather expensive wafers, e.g., silicon on insulator wafers, which are also used for device production, are employed as test wafers. Conventionally, the ion-implantation monitoring using implant monitor test wafers requires one wafer per implant species, implantation dose, implantation depth, and test-run.
With reference to FIGS. 1a and 1b, an illustrative example of implanting ions into a lightly doped silicon wafer according to a typical prior art process will be described. It is to be noted that FIGS. 1a and 1b as well as the following drawings in this application are merely schematic depictions of the various stages in manufacturing the illustrative device under consideration. The skilled person will readily appreciate that the dimensions shown in the figures are not true to scale and that different portions or layers are not separated by sharp boundaries as portrayed in the drawings but may instead comprise continuous transitions. Furthermore, various process steps as described below may be performed differently depending on particular design requirements. Moreover, in this description, only the relevant steps and portions of the device necessary for understanding the present invention are considered.
FIG. 1a shows a schematic cross-sectional view of a wafer 101 comprising a silicon substrate 102 with a surface 103, whereby the silicon substrate 102 is lightly doped with a first species of implanted ions. According to a conventional implantation process 104 a second species of ions, which is a counterdoping species to the first species, is implanted through surface 103 into the wafer 101 with an implantation dose until a desired implantation depth is reached. For activation of the second species of ions, i.e., building the newly implanted ions into the lattice of the wafer 101 by means of substitution, an anneal must be applied to the wafer 101.
FIG. 1b shows a schematic cross-sectional view of the wafer 101 after ion-implantation and RTA annealing. An implanted layer 105 comprising the second species of ions is formed in the wafer 101 according to the above-mentioned implantation process 104. Between the implanted layer 105 and the silicon substrate 102 a pn-junction 106 is formed in the desired implantation depth. After the annealing step, sheet-resistance of the substrate is measured by local four-point-probe measurements distributed across the whole substrate to determine implantation characteristics, and, in particular, homogeneity. After implantation characteristics are obtained, the substrate is discarded according to the prior art.
Consequently, there is a great overall test wafer consumption during manufacturing of semiconductor devices. This test wafer consumption is a significant contributor to the cost of manufacturing in semiconductor industry mainly due to scrapping the test wafers after only one instance of monitoring the implantation parameters. Therefore, there is a great desire to reduce the overall test wafer consumption and, accordingly, the cost of manufacturing.
The present invention provides a method of reusing ion-implantation test wafers for monitoring implantation parameters.
According to a first embodiment of the present invention, a method of monitoring implantation parameters for characterization of an implantation apparatus is provided, the method comprising providing a substrate for use as a test wafer for monitoring the implantation parameters, implanting first ions into the substrate, and annealing the substrate with the first ions implanted. The method also comprises obtaining the implantation parameters by measuring implantation-dependent characteristics of the substrate with the first ions implanted, implanting second ions into the substrate with the first ions implanted, and annealing the substrate with the first and second ions implanted. The method further comprises obtaining the implantation parameters by measuring implantation-dependent characteristics of the substrate with the first and second ions implanted, reusing the substrate for a further parameter-measuring process.
According to a second embodiment of the present invention, a method of monitoring implantation parameters for characterization of an implantation apparatus is provided, the method comprising providing a substrate for use as a test wafer for monitoring the implantation parameters, implanting first ions of a first species into the substrate, and annealing the substrate with the first ions implanted. The method also comprises obtaining the implantation parameters by measuring implantation-dependent characteristics of the substrate with the first ions implanted, implanting second ions of a second species into the substrate with the first ions implanted, and annealing the substrate with the first and second ions implanted. The method further comprises obtaining the implantation parameters by measuring implantation-dependent characteristics of the substrate with the first and second ions implanted, reusing the substrate for a further parameter-measuring process.
According to this second embodiment of this invention, the second ion-implantation is of a different implant species from the first ion-implantation. If, in addition, varying implantation conditions are used, alternating pn-junctions with successively decreasing junction-depth are created in the test wafer. Since the pn-junctions isolate the underlying substrate from the wafer surface, only the characteristics of the top implantation layer are subject to electrical measurement.
According to a third embodiment of the present invention, a method of monitoring implantation parameters for characterization of an implantation apparatus is provided, the method comprising providing a substrate for use as a test wafer for monitoring the implantation parameters, implanting first ions of a first species into the substrate, and annealing the substrate with the first ions implanted. The method also comprises obtaining the implantation parameters by measuring implantation-dependent characteristics of the substrate with the first ions implanted, implanting second ions of the first species into the substrate with the first ions implanted, and annealing the substrate with the first and second ions implanted. The method further comprises obtaining the implantation parameters by measuring implantation-dependent characteristics of the substrate with the first and second ions implanted, reusing the substrate for a further parameter-measuring process.
According to this third embodiment of this invention, the second ion-implantation uses the same implant species as the first ion-implantation, and identical implanting and annealing conditions. This method enables a reusing of the test wafer until the sheet-resistance sensitivity starts to degrade by dopant saturation. This method may be applied to any known implant species.
As a result of the present invention, there is a significant cost-reduction in implant-areas of the semiconductor device manufacturing industries, due to reusing the expensive test wafers.